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Silicon Labs /Series0 /EFM32HG /EFM32HG210F64 /MSC /READCTRL

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Interpret as READCTRL

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https://regviz.com/r/Silicon Labs/Series0/EFM32HG/EFM32HG210F64/MSC/READCTRL#0x0

31282724232019161512118743000000000000000000000000000000000000000000 (WS0)MODE0 (IFCDIS)IFCDIS0 (AIDIS)AIDIS0 (RAMCEN)RAMCEN

MODE=WS0

Description

Read Control Register

Fields

MODE

Read Mode

0 (WS0): Zero wait-states inserted in fetch or read transfers.

1 (WS1): One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz.
IFCDIS

Internal Flash Cache Disable
AIDIS

Automatic Invalidate Disable
RAMCEN

RAM Cache Enable

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data